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Multi-Protocol Engine with Classifier, Look-Aside, 5-10 Gbps
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APB SPI (Serial Peripheral Interface) master and slave
The eSi-SPI core is a Serial Peripheral Interface that can be used to implement full-duplex, synchronous, serial communications between ICs. The eSi-SPI core can operate as a SPI master or slave. Multiple chip-selects are supported in master mode, to allow connection to multiple slave devices. The SPI is supplied with an AMBA APB slave interface and so can be driven by software or via DMA.
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Block Diagram of the APB SPI (Serial Peripheral Interface) master and slave
