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ARC-V RHX-100 dual-issue, 32-bit single-core RISC-V processor for real-time applications
The Synopsys ARC-V™ RHX-100 series processors feature a dual-issue, 32-bit superscalar architecture for use in applications where real-time performance is required. The cores offer outstanding performance delivering with a small area footprint and low power consumption.
The ARC-V RHX-100 processors are based on the RISC-V instruction set architecture (ISA). The processors feature a 34-bit physical address
space defined by the RISC-V Sv32 MMU. For applications requiring higher performance, the multi-core RHX-105 and RHX-105V are available with up to 16 CPU cores and up to 16 hardware accelerators in the processor cluster. RISC-V vector extensions (RVV) are available in the RHX-100V (single core) and RHX-105V (multi-core) processors.
The ARC-V RHX-100 features level 1 (L1) instruction and data cache and close coupled memory (CCM) and is optimized for use in high-performance real-time embedded applications.
The ARC-V RHX-100 processors are based on the RISC-V instruction set architecture (ISA). The processors feature a 34-bit physical address
space defined by the RISC-V Sv32 MMU. For applications requiring higher performance, the multi-core RHX-105 and RHX-105V are available with up to 16 CPU cores and up to 16 hardware accelerators in the processor cluster. RISC-V vector extensions (RVV) are available in the RHX-100V (single core) and RHX-105V (multi-core) processors.
The ARC-V RHX-100 features level 1 (L1) instruction and data cache and close coupled memory (CCM) and is optimized for use in high-performance real-time embedded applications.
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