USB-C 3.1 SS/SSP PHY in Type-C in TSMC (16nm, 12nm, N7, N6, N5, N5A)
Arm Cortex-M0+
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Block Diagram of the Arm Cortex-M0+ IP Core
Arm IP
- InCore Calcite Series: 32b/64b RISC-V 5-stage, scalar, in-order, Application Processor. Linux and multi-core capable. Maps upto ARM A-35. Optimal PPA.
- InCore Azurite Series: 32b/64b RISC-V 2-stage, scalar, in-order, Embedded Processor. RTOS and multi-core capable. Maps upto ARM M-4F. Optimal PPA.
- Quad core IP platform with integrated Arm security subsystem
- ARM HSSTP PHY with Link Layer
- LC3 / LC3plus Bluetooth LE Audio Codecs for Arm Cortex M4 & M33
- LC3 / LC3plus Bluetooth LE Audio Codecs for Arm Cortex M55