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ARM System Controller
Features
- Designed for ASIC and PLD implementations.
- Fully static design with edge triggered flip-flops.
- Supports ARM microprocessors.
- Fully integrated single chip design provide complete system level functions for all external data access.
- Replaces multiple discrete devices on the system.
- Flexible design adaptive to different system requirements.
- Two different clock domains for CPU and PCI bus interface.
- Supports concurrent data transfer between CPU, System memory, DMA and PCI bus.
- System control register distributed in each functional blocks.
- On-chip connection to user-defined logic blocks.
- PCI spec 2.2 compliant.
- Supports industrial standard SDRAMs.
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ARM System Controller ahb IP
- AHB system Peripheral IP, SDRAM controller, Soft IP
- AHB system Peripheral IP, SRAM controller, Soft IP
- AHB system Peripheral IP, External Bus controller, Soft IP
- AHB system Peripheral IP, SRAM/ROM Controller, Soft IP
- AHB system Peripheral IP, Interrupt controller, Soft IP
- I2C/SMBus Master/Slave Controller w/FIFO (AXI/AHB/APB)