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AXI4 to/from Stream DMA
The AXI4-DMA IP core implements a Direct Memory Access (DMA) engine that efficiently moves data between AXI4-Stream peripherals and a memory-mapped AXI4 bus.
The core implements two independent paths: One transfers data from the read manager memory-mapped interface to the manager stream (MM2S) interface. The other transfers data from the subordinate stream interface to the write manager memory-map (S2MM) interface. Each path consists of a data mover block, the control-and-status registers, and buffers for DMA commands and responses. The host system can program the commands and receives responses via the control and status registers (CSR) interface. The address offset for each DMA command is either 32- or 64-bits wide, and the length of the transfer is 16 bits, allowing up to 64kB to be transferred with a single command. The MM2S commands control the behavior of the TLAST and TUSER signals of the manager stream interface, while TLAST on the subordinate stream interface causes an early termination of the transaction. The data-movers use the response descriptors to report possible errors and the actual transfer length for the S2MM path.
Designed for ease of integration, the AXI4-DMA supports configuration options and optional modules allowing the adoption of the core to the requirements of each specific design. The data-bus and address-bus widths of the AXI4 interfaces and the data-bus width of the AXI4-stream interfaces are synthesis-time configurable and can be 32 or 64 bits. External AXI-Stream data width converters can connect to peripherals with wider or narrower data-buses, The core is delivered with such sample modules converting from 32 bits to 64 bits and vice-versa. Furthermore, integration with a 32-bit AHB bus is possible with the AXI-to-AHB bridge that is also included.
The AXI4-DMA core is rigorously verified, LINT-clean, and scan-ready. It is available in synthesizable Verilog and FPGA netlist forms and includes everything required for successful implementation, including a UVM testbench, simulation and synthesis scripts, and comprehensive user documentation.
The core implements two independent paths: One transfers data from the read manager memory-mapped interface to the manager stream (MM2S) interface. The other transfers data from the subordinate stream interface to the write manager memory-map (S2MM) interface. Each path consists of a data mover block, the control-and-status registers, and buffers for DMA commands and responses. The host system can program the commands and receives responses via the control and status registers (CSR) interface. The address offset for each DMA command is either 32- or 64-bits wide, and the length of the transfer is 16 bits, allowing up to 64kB to be transferred with a single command. The MM2S commands control the behavior of the TLAST and TUSER signals of the manager stream interface, while TLAST on the subordinate stream interface causes an early termination of the transaction. The data-movers use the response descriptors to report possible errors and the actual transfer length for the S2MM path.
Designed for ease of integration, the AXI4-DMA supports configuration options and optional modules allowing the adoption of the core to the requirements of each specific design. The data-bus and address-bus widths of the AXI4 interfaces and the data-bus width of the AXI4-stream interfaces are synthesis-time configurable and can be 32 or 64 bits. External AXI-Stream data width converters can connect to peripherals with wider or narrower data-buses, The core is delivered with such sample modules converting from 32 bits to 64 bits and vice-versa. Furthermore, integration with a 32-bit AHB bus is possible with the AXI-to-AHB bridge that is also included.
The AXI4-DMA core is rigorously verified, LINT-clean, and scan-ready. It is available in synthesizable Verilog and FPGA netlist forms and includes everything required for successful implementation, including a UVM testbench, simulation and synthesis scripts, and comprehensive user documentation.
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Block Diagram of the AXI4 to/from Stream DMA IP Core
