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400G ultra low latency 56/112G FEC and SERDES IP sub 10ns latency
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Band-gap Reference in GF N65 LP. Multiple voltages referenced to internal and external resistors.
The PMCC_REFS IP block combines two modules of GM current references and one module of BG (band-gap) current reference. Each module provides up to twelve of each: 50µA, 20µA and 10µA stabilized current outputs. The Band-gap reference and one of the GM references provide output current proportional to 1/Rinternal. Another GM referenced provides output current proportional to 1/Rexternal.
The biasing currents are programmable within +/-30% permitting the block parameter changing, power minimization for given performance or operational margin estimation in production. Layout is designed using IBM CMOS10LPE 5_01_00_01_LD metal stack. Control functions and layout configuration can be customized upon special agreement.
The biasing currents are programmable within +/-30% permitting the block parameter changing, power minimization for given performance or operational margin estimation in production. Layout is designed using IBM CMOS10LPE 5_01_00_01_LD metal stack. Control functions and layout configuration can be customized upon special agreement.
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Band-gap IP
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