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Cache controller including Retention Ready feature for fast CPU wake-up time and very low power consumption
R-Stratus-LPRR is an updated release of cache controller for MCU based on Non Volatile Memories (NVM) like eFlash or EEPROM.
R-Stratus LPRR update consist in retainin the last 4x cache line accessed thus increasing the number of Hit 0 (get data from cache) ratio vs Hit 1 (read tag before getting data from cache). It provides the twofold advantage of speed improvement and of power consumption minimization. It is AMBA 3 AHB-lite compliant.
R-Stratus LPRR includes a Retention Ready feature to allow fast CPU wake-up from deep sleep mode.
R-Stratus LPRR update consist in retainin the last 4x cache line accessed thus increasing the number of Hit 0 (get data from cache) ratio vs Hit 1 (read tag before getting data from cache). It provides the twofold advantage of speed improvement and of power consumption minimization. It is AMBA 3 AHB-lite compliant.
R-Stratus LPRR includes a Retention Ready feature to allow fast CPU wake-up from deep sleep mode.
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Block Diagram of the Cache controller including Retention Ready feature for fast CPU wake-up time and very low power consumption
Cache Controller IP
- Cache controller including Retention Ready feature for fast CPU wake-up time and very low power consumption
- 64-bit CPU Core with Level-2 Cache Controller
- AHB Cache Controller Core
- Cache controller for fast NVM memories access and very low power consumption
- AXI system Peripheral IP, Cache Controller, L2 Cache, Soft IP
- Compute Express Link (CXL) 2.0 Controller with AMBA AXI interface