Centralised Real Time Processor IP Core
The CryptOne IP core's energy-efficient design makes it possible to use a very compact silicon footprint with fast computation. Numerous interfaces, such as AMBA AHB, AXI4, and APB, are available for it. System integration is simple and quick because to the highly intuitive interface. The core has optional DPA countermeasures and is immune to timed assaults. The universal and completely scalable
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Block Diagram of the Centralised Real Time Processor IP Core
![Centralised Real Time Processor IP Core Block Diagam](http://www.design-reuse.com/sip/blockdiagram/54202/20240524114510-main-CRP1A-IP-Core.png)
CRP1A Encryption/Decryption IP
- AES-XTS encryption/decryption IP
- DES and Triple DES (TDES or 3DES) encryption and decryption coprocessor
- Cryptographic library for encryption and decryption of Advanced Encryption Standard (AES) in ECB, CBC, OFB, CTR and GCM modes
- Java Card compliant cryptographic library for encryption and decryption of RSA, DSA, Diffie-Hellman, El-Gamal and Elliptic Curves algorithms
- Secure key computation, encryption, decryption, signature and verification functionalities compliant with the PKCS#1
- SHA-256 encryption and decryption coprocessor