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Coherent Network-on-chip (NoC) IP
C-NoC is a layered, scalable, configurable, and physically aware configurable NoC. It supports mesh, grid and torus topologies with simultaneous existence of both coherent and non-coherent traffic. It has configurable data bus widths, supports multiple clocking schemes, and is physically-aware with auto-pipelining and grouping of routers to meet timing requirements. C-NoC supports multiple protocols including CHI, AXI4/3 and AXI-lite, ACE and ACE-lite.
C-NoC provides power control through power-islanding and a power-gating architecture at the interface port and router level, and is physically aware with automated insertion and deletion of pipelines to meet timing, generation of placement-aware groups and topologies, and power and frequency aware NoC generation.
C-NoC provides high performance with on-chip L3 cache support to reduce memory access latency, and its pipeline architecture provides scalability with maximum throughput and minimum latency. It is parity enabled to provide resiliency.
C-NoC provides power control through power-islanding and a power-gating architecture at the interface port and router level, and is physically aware with automated insertion and deletion of pipelines to meet timing, generation of placement-aware groups and topologies, and power and frequency aware NoC generation.
C-NoC provides high performance with on-chip L3 cache support to reduce memory access latency, and its pipeline architecture provides scalability with maximum throughput and minimum latency. It is parity enabled to provide resiliency.
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Block Diagram of the Coherent Network-on-chip (NoC) IP IP Core
