Compact Implementation of the RISC-V RV32EMC ISA

Cortus have applied their many years of processor design expertise to the RISC-V ISA. Concentrating on the needs of the embedded designer and leveraging the success of their APS family of processors.

The APS3V processor offers the RISC-V ISA RV32EMC features, with the full integer instruction set, compressed instructions and multiply and divide. In addition it implements the privilege features with Machine and User modes.

The Cortus APS1V processor is designed to be both power and silicon efficient. The standard implementation requires 12 634 gates.

The Cortus APS1V processor features a Harvard architecture with AXI4 Lite bus interfaces. This ensures wide compatibility with other peripheral IP, allowing the standard peripherals from Cortus to be complemented by other IP.

Full debug support is implemented through Cortus’ standard debug interface and tools (GDB and OpenOCD).

• see the entire Compact Implementation of the RISC-V RV32EMC ISA datasheet
• get in contact with Compact Implementation of the RISC-V RV32EMC ISA Supplier