Compact, Secure and Performance Efficiency 32-bit RISC-V Core

AndesCore™ D23 is a 32-bit 3-stage pipeline CPU IP core based on AndeStar™ V5/V5e architecture for embedded applications with small gate count, and some dual-issue ability. In addition to commonly used RISC-V I/EMAC, single/double precision FPU and DSP extensions, it supports the recently ratified ISA extensions such as B (bit manipulation), K (scalar cryptography), and CMO (cache management operations) as well as Zce draft (code size reduction). The D23 implements ePMP and sPMP to improve core security; PPMA for on-the-fly change of memory attributes; and Andes V5 extensions that include StackSafe™ (for hardware stack protection), CoDense™, PowerBrake and WFI/WFE. The D23 supports both four-wire and two-wire JTAG debug and instruction trace interface for software development. On the performance front, it deploys several configurable options such as dynamic branch prediction, caches and local memories, multiplier optimized for performance or area. Moreover, it comes with rich features to ease SoC integration such as CLIC and PLIC for interrupt handling; an AHB-Lite system bus and an AHB-Lite low-latency interface; an APB bus for CPU local peripherals, and an AHB-Lite local memory access port for external bus masters. Some of the features will be implemented in CPU revision update, details below.

• see the entire Compact, Secure and Performance Efficiency 32-bit RISC-V Core datasheet
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