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ComputeRAM
ComputeRAM is an SRAM macro with integrated compute capability. It is a semiconductor IP product designed to enable microcontroller-based systems to run AI, DSP, and other linear algebra routines up to 130x faster and 150x more energy efficiently.
ComputeRAM enables licensees to seamlessly integrate in-memory computing capabilities into existing chip designs. A ComputeRAM macro shares the same memory interface as conventional SRAM and is compatible with any microcontroller-based SoC (Arm, RISC-V, x86, or otherwise).
ComputeRAM’s SDK allows programmers to develop and port new and existing libraries to a ComputeRAM-enabled system. Running linear algebra-intensive applications on a ComputeRAM-based system results in dramatic performance gains, as shown in the plot below. When users implement a 64x256 matrix-vector product (non-sparse, 8b weight/8b input) on an Arm Cortex-M0 using ComputeRAM instead of standard SRAM, post-synthesis gate-level simulation results at typical operating conditions (25 degrees C, 0.8V VCS) result in improvements of up 130x in latency and 150x in energy efficiency. The code snippet highlights how ComputeRAM can be easily programmed as conventional memory and for computation.
The SDK also includes libraries of ComputeRAM-optimised AI and DSP building blocks. Simulation results using the MLPerf™ Tiny benchmarks, at typical operating conditions, show that a ComputeRAM-enabled low-footprint microcontroller achieves improvements of up to 32x in energy efficiency and 30x in latency compared to the best-performing AI accelerator submission (GAP9 EVK N31 for the Anomaly Detection benchmark).
ComputeRAM enables licensees to seamlessly integrate in-memory computing capabilities into existing chip designs. A ComputeRAM macro shares the same memory interface as conventional SRAM and is compatible with any microcontroller-based SoC (Arm, RISC-V, x86, or otherwise).
ComputeRAM’s SDK allows programmers to develop and port new and existing libraries to a ComputeRAM-enabled system. Running linear algebra-intensive applications on a ComputeRAM-based system results in dramatic performance gains, as shown in the plot below. When users implement a 64x256 matrix-vector product (non-sparse, 8b weight/8b input) on an Arm Cortex-M0 using ComputeRAM instead of standard SRAM, post-synthesis gate-level simulation results at typical operating conditions (25 degrees C, 0.8V VCS) result in improvements of up 130x in latency and 150x in energy efficiency. The code snippet highlights how ComputeRAM can be easily programmed as conventional memory and for computation.
The SDK also includes libraries of ComputeRAM-optimised AI and DSP building blocks. Simulation results using the MLPerf™ Tiny benchmarks, at typical operating conditions, show that a ComputeRAM-enabled low-footprint microcontroller achieves improvements of up to 32x in energy efficiency and 30x in latency compared to the best-performing AI accelerator submission (GAP9 EVK N31 for the Anomaly Detection benchmark).
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Block Diagram of the ComputeRAM IP Core
