Config of FDDR, SERDES; incl Fabric Master Mode

CoreSF2Config facilitates the configuration of peripheral blocks in a SmartFusion®2 device, including the microcontroller subsystem (MSS) double data rate (DDR) controller, known as the MDDR, fabric DDR (FDDR) controller, and high speed serial interface blocks (SERDESIF). CoreSF2Config has a mirrored master advanced peripheral bus (APB) port and several mirrored slave APB ports. The mirrored master APB port should be connected to the FIC_2_APB_MASTER master port of MSS and the mirrored slave APB ports should be connected to the APB slave ports of the blocks that need to be configured.

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