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Core generator for finite impulse response filters
CoreFIR is a core generator for finite impulse response (FIR) filters. The core generator uses a distributed arithmetic implementation methodology to create FPGA-based digital filters.
The FIR filter is one of the most essential building blocks in DSP systems. Many systems use digital filters to remove unwanted noise, improve signal quality, or shape signal spectrum. The Microsemi CoreFIR provides a highly configurable area-efficient, high-performance FIR filter that utilizes hard multiplier-accumulator (MAC) blocks available on RTAX-DSP devices. The core generates the RTL code of the filter in Verilog and VHDL languages.
The core implements a range of filter types:
* Single rate Fully Enumerated (parallel)
* Single rate Folded (semi-parallel) filter
* Multi-rate Polyphase Interpolation FIR filter
CoreFIR v8.5 Features:
* Performance up to 124 MHz in the following RTAX-DSP devices:
* RTAX2000D
* RTAX4000D
* Supports up to 1024 FIR filter taps
* Run-time reloadable coefficients, multiple coefficient sets, or fixed coefficients
* 2 to 18-bit input data and coefficient precision
* Signed or unsigned data and coefficients
* Full precision output
* Coefficient symmetry optimization (on the fully enumerated filters)
* Supports SmartFusion2, IGLOO2h4CoreFIR (legacy version 3.0 — download Core Generator below)
The previous legacy CoreFIR version is also available for download for fabric-only FIR applications in Microsemi flash and antifuse FPGA device families.
CoreFIR v3.0 (legacy) Features:
* Two FIR Computation Algorithms for Design flexibility
* Constant Coefficient (CC) Algorithm for High Throughput
* Constant Multiplier Computation, Low Gate Counts and High Speed
* Distributed Arithmetic (DA) Algorithm
* Multiplier-Free Computation
* Efficient DA Architecture using Embedded RAM Lookup Tables
* Folding architecture with serialized computation to minimize size for Lower sample rates
* Multiple DA Lookup Tables to Split Large number of Taps
* Core Generator
* Executable File Outputs Runtime Library (RTL)
* Self-Checking: Executable tests generate output against the algorithm
* Supports 2 to 128 Taps and 1- to 32-Bit input data
The FIR filter is one of the most essential building blocks in DSP systems. Many systems use digital filters to remove unwanted noise, improve signal quality, or shape signal spectrum. The Microsemi CoreFIR provides a highly configurable area-efficient, high-performance FIR filter that utilizes hard multiplier-accumulator (MAC) blocks available on RTAX-DSP devices. The core generates the RTL code of the filter in Verilog and VHDL languages.
The core implements a range of filter types:
* Single rate Fully Enumerated (parallel)
* Single rate Folded (semi-parallel) filter
* Multi-rate Polyphase Interpolation FIR filter
CoreFIR v8.5 Features:
* Performance up to 124 MHz in the following RTAX-DSP devices:
* RTAX2000D
* RTAX4000D
* Supports up to 1024 FIR filter taps
* Run-time reloadable coefficients, multiple coefficient sets, or fixed coefficients
* 2 to 18-bit input data and coefficient precision
* Signed or unsigned data and coefficients
* Full precision output
* Coefficient symmetry optimization (on the fully enumerated filters)
* Supports SmartFusion2, IGLOO2h4CoreFIR (legacy version 3.0 — download Core Generator below)
The previous legacy CoreFIR version is also available for download for fabric-only FIR applications in Microsemi flash and antifuse FPGA device families.
CoreFIR v3.0 (legacy) Features:
* Two FIR Computation Algorithms for Design flexibility
* Constant Coefficient (CC) Algorithm for High Throughput
* Constant Multiplier Computation, Low Gate Counts and High Speed
* Distributed Arithmetic (DA) Algorithm
* Multiplier-Free Computation
* Efficient DA Architecture using Embedded RAM Lookup Tables
* Folding architecture with serialized computation to minimize size for Lower sample rates
* Multiple DA Lookup Tables to Split Large number of Taps
* Core Generator
* Executable File Outputs Runtime Library (RTL)
* Self-Checking: Executable tests generate output against the algorithm
* Supports 2 to 128 Taps and 1- to 32-Bit input data
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