CSMC 0.13um 1.2v/3.3v APLL

This IP is a programmable Analog PLL suitable for high speed clock generation. The high speed VCO can run from 100MHz to 300MHz. It contains a 1-32 input clock divider, a 1-64 feedback clock divider and a 1-8 output clock divider. By setting DM [4:0], DN [5:0] and DP [2:0] to different values according to different REFIN, CLK and CLKO will be locked at the multiples of the input frequency.

• see the entire CSMC 0.13um 1.2v/3.3v APLL datasheet
• get in contact with CSMC 0.13um 1.2v/3.3v APLL Supplier