DDR3/2 PHY

The DDR3/2 PHY is a complete mixed-signal IP solution designed to provide DDR 3/2 SDRAM connectivity in a System-On-a-Chip (SOC) design targeted to a specific fabrication process. The DDR3/2 PHY supports a range of DDR3 SDRAM speeds, from DDR3-667 through DDR3-1600, with backward compatibility provided for DDR2-667 through DDR2-1066 devices. Targeted toward supporting x8 and x16 DDR3 SDRAM components, DDR3/2 PHY supports interfaces of varying widths, from a minimum of 8 bits wide, in 8-bit increments. Delivered to customers as hardened IP components— Address/Command, DATX8, and SSTL I/O Library—implementations of the DDR3/2 PHY are compatible with JEDEC DDR2 and DDR3 SDRAMs, helping ensure customer success.

• see the entire DDR3/2 PHY datasheet
• get in contact with DDR3/2 PHY Supplier