English
You are here:
DDR3/DDR2/LPDDR2 COMBO Interface
Features
- DDR3/DDR2/LPDDR2 COMBO interface for DRAM application
- SMIC 40nm Logic Low Leakage Salicide 1.1V/1.8V/2.5V Process
- Cell Size (Width * height) 30um * 280um with DUP stagger bonding pads
- Work IO voltage: 1.2V/1.5V/1.8V
- Programmable driven-strength, programmable ODT,support DDR3-1333,DDR2-1066,LPDDR2-1066
- Suitable for 8 layer application
View DDR3/DDR2/LPDDR2 COMBO Interface full description to...
- see the entire DDR3/DDR2/LPDDR2 COMBO Interface datasheet
- get in contact with DDR3/DDR2/LPDDR2 COMBO Interface Supplier
IO IP
- ONFI 4.1 NAND Flash Controller & PHY & IO Pads on 16nm
- TSMC 3nm (N3E) 1.8V SD/eMMC IO
- ONFI 4.1 NAND Flash Controller & PHY & IO Pads on 12nm
- ONFI 4.1 NAND Flash Controller & PHY & IO Pads on 28nm
- 2-16Gbps Multi-Protocol IO Supporting BOW, OHBI and UCIe
- LVDS IO handling data rate up to 50Mbps with maximum loading 60pF