English
You are here:
DDR3 SDRAM Memory Controller
The logiMEM DDR3 SDRAM Memory Controller is a size optimized, flexible, parametric and synthesizable Synchronous DRAM Controller that supports industry standard Double Data Rate 3 (DDR3) SDRAM memories on AMD-Xilinx 7 Series FPGAs/SoCs. Its system interface is compliant to ARM’s AMBA® Advanced eXtensible Interface (AXI4) protocol.
“Easy-to-use” parameters and the synthesis for different requirements, optimized for area and speed, auto-routed design makes this IP Core especially suitable for AMD-Xilinx 7 Series FPGA/SoC designs featuring AXI4 bus architecture. It enables an easy connection of processor cores, as well as various peripheral cores, to DDR3 memory chips via AXI4 slave system interface port.
The logiMEM IP Core is fully embedded into the AMD-Xilinx Vivado toolset, and its parametrizable VHDL design allows tuning of slice consumption and features set through an easy-to-use GUI interface. The logiMEM can be smoothly integrated with other logicBRICKSTM IP cores for building of advanced GUI embedded systems.
“Easy-to-use” parameters and the synthesis for different requirements, optimized for area and speed, auto-routed design makes this IP Core especially suitable for AMD-Xilinx 7 Series FPGA/SoC designs featuring AXI4 bus architecture. It enables an easy connection of processor cores, as well as various peripheral cores, to DDR3 memory chips via AXI4 slave system interface port.
The logiMEM IP Core is fully embedded into the AMD-Xilinx Vivado toolset, and its parametrizable VHDL design allows tuning of slice consumption and features set through an easy-to-use GUI interface. The logiMEM can be smoothly integrated with other logicBRICKSTM IP cores for building of advanced GUI embedded systems.
View DDR3 SDRAM Memory Controller full description to...
- see the entire DDR3 SDRAM Memory Controller datasheet
- get in contact with DDR3 SDRAM Memory Controller Supplier
Block Diagram of the DDR3 SDRAM Memory Controller IP Core
