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Direct Memory Access Controller IP Core
The DMA_CTRL core implements a low-power, single-channel Direct Memory Access (DMA) controller that is used to transfer data across a bus to and from a peripheral device.
With the DMA_CTRL, a DMA transfer can be initiated by software (via register access), or via a dedicated DMA-request pin that can be driven by a peripheral or other hardware module. The latter makes the core suitable for low-power systems where, in order to preserve power, it may be desirable to transfer data up on a schedule or when an event occurs, without waking up the CPU.
The DMA_CTRL configuration and status registers are accessible via a 32-bit host slave interface. The protocol for the host slave interface is configurable at synthesis time, and the user can choose between a Wishbone, AXI Lite, or APB interface. The core’s registers are used to configure the DMA transfer parameters, such as the number of bytes to be transferred, transfer direction, address offsets, bus addressing mode and burst size. The core also reports possible transfer status and possible bus errors to its status registers.
The core has two 32-bit master interfaces for transferring data: the one reads data from the source location and the other writes data to the destination location. The protocol for each master port is configurable at synthesis time, and the user can choose between a Wishbone, AXI, or AHB interface. The direction of the transfer is run-time programmable, and the user can choose to implement a different protocol for each interface. This means that the DMA_CTRL core can be used to transfer data between different buses (e.g. AHB and AXI, or AXI to Wishbone). If the same protocol is used for both master ports, then the two ports can be externally arbitrated and be connected to a single master port of the interconnect fabric.
The DMA_CTRL core is rigorously verified, silicon-proven, and available in RTL Verilog source or as a targeted FPGA netlist.
With the DMA_CTRL, a DMA transfer can be initiated by software (via register access), or via a dedicated DMA-request pin that can be driven by a peripheral or other hardware module. The latter makes the core suitable for low-power systems where, in order to preserve power, it may be desirable to transfer data up on a schedule or when an event occurs, without waking up the CPU.
The DMA_CTRL configuration and status registers are accessible via a 32-bit host slave interface. The protocol for the host slave interface is configurable at synthesis time, and the user can choose between a Wishbone, AXI Lite, or APB interface. The core’s registers are used to configure the DMA transfer parameters, such as the number of bytes to be transferred, transfer direction, address offsets, bus addressing mode and burst size. The core also reports possible transfer status and possible bus errors to its status registers.
The core has two 32-bit master interfaces for transferring data: the one reads data from the source location and the other writes data to the destination location. The protocol for each master port is configurable at synthesis time, and the user can choose between a Wishbone, AXI, or AHB interface. The direction of the transfer is run-time programmable, and the user can choose to implement a different protocol for each interface. This means that the DMA_CTRL core can be used to transfer data between different buses (e.g. AHB and AXI, or AXI to Wishbone). If the same protocol is used for both master ports, then the two ports can be externally arbitrated and be connected to a single master port of the interconnect fabric.
The DMA_CTRL core is rigorously verified, silicon-proven, and available in RTL Verilog source or as a targeted FPGA netlist.
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Block Diagram of the Direct Memory Access Controller IP Core
DMA Controller IP
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