English
Aeonic Generate Digital PLL for multi-instance, core logic clocking
You are here:
Distributed Memory Generator
The Distributed Memory Generator is provided under the terms of the Xilinx End User License and is included with ISE® and Vivado™ design tools at no additional charge.
The Distributed Memory Generator IP core creates a variety of memory structures using Select RAM. It can be used to create Read Only Memory (ROM), single-port Random Access Memory (RAM), and simple dual/Dual port RAM as well as SRL16-based RAM. Flexible feature set allows users to customize for Memory type, Data width, Memory size, Input/Output options and reset options.
The Distributed Memory Generator IP core creates a variety of memory structures using Select RAM. It can be used to create Read Only Memory (ROM), single-port Random Access Memory (RAM), and simple dual/Dual port RAM as well as SRL16-based RAM. Flexible feature set allows users to customize for Memory type, Data width, Memory size, Input/Output options and reset options.
View Distributed Memory Generator full description to...
- see the entire Distributed Memory Generator datasheet
- get in contact with Distributed Memory Generator Supplier