Aeonic Generate Digital PLL for multi-instance, core logic clocking
Dual channel 12-bit, 640MS/s ADC IP for WIFI6 in TSMC 22nm
View Dual channel 12-bit, 640MS/s ADC IP for WIFI6 in TSMC 22nm full description to...
- see the entire Dual channel 12-bit, 640MS/s ADC IP for WIFI6 in TSMC 22nm datasheet
- get in contact with Dual channel 12-bit, 640MS/s ADC IP for WIFI6 in TSMC 22nm Supplier
A/D IP
- FlexNoC Functional Safety (FuSa) Option helps meet up to ISO 26262 ASIL B and D requirements against random hardware faults.
- 12-bit 50/100MSPS SAR A/D Converter in 55nm LL
- 2D Vector Graphics Accelerator / GPU (Graphics Processing Unit)
- 2D/3D Vector Graphics Accelerator / GPU (Graphics Processing Unit)
- 3D OpenGL ES GPU (Graphics Processing Unit)
- JESD204D