400G ultra low latency 56/112G FEC and SERDES IP sub 10ns latency
Dual RSDS Transmitter, 30-bit color, 80-400Mb/s (SVGA/Full HDTV@120Hz)
The transmitter converts up to 30-bit DDR CMOS data (single pixel 24-bit, single pixel 30-bit, dual pixel 24-bit, dual pixel 30-bit color) into 30 RSDS, (Reduced Swing Differential Signaling) data streams.
At a maximum dual pixel rate of 200Mhz, RSDS data line speed is 400Mbps, providing a total throughput of 12Gbps (1.5GygaBytes per second).
All the data input/output are independent from each other and can be assigned following any partitioning to support all LCD and Plasma display panel system architectures. (RGB, front/back, even/odd, mixed RGB etc…)
Each pixel channel has 3 identical clock outputs. Strength of the RSDS I/Os can be adjusted from 2mA nominal to 4mA in order to support both 100 and 50 termination. Tree extra clock output are also provided.
For convenient routing when TCON is mounted on top or bottom of a display panel, a selectable output data mapping is usually available. LSB or MSB of both channels can be forced to High-Z in order to support 24-bit data color.
This IP can interface with both 1.2V or 3.3V core logic, giving more flexibility for the design.
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