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MIPI D-PHY Tx-Only 2 Lanes in TSMC (28nm, 22nm, 16nm, 12nm, N7, N6)
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ECC_56_32_4
ECC_56_32_4 engine is implemented using BCH algorithm to correct up to 4 errors and detect errors greater than 4 bits. It operates by adding ECC check bits to data bits during the encoding process.
During decoding process, ecc code word, comprising of data bits and check bits are analyzed by syndrome generation & checking. If any errors are detected, then further processing is done to identify error locations. In the next step, checks are performed for mis-corrections due to errors beyond the capability of ECC decoder.
Mis-correction probability is “0” for any errors less than the correction capability, but mis-correction probability is non-zero for errors greater than the error correction probability
During decoding process, ecc code word, comprising of data bits and check bits are analyzed by syndrome generation & checking. If any errors are detected, then further processing is done to identify error locations. In the next step, checks are performed for mis-corrections due to errors beyond the capability of ECC decoder.
Mis-correction probability is “0” for any errors less than the correction capability, but mis-correction probability is non-zero for errors greater than the error correction probability
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Block Diagram of the ECC_56_32_4 IP Core
