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Ethernet PCS 100G
Comcores PCS 100G IP core is a silicon agnostic implementation of the Physical Coding Sublayer (PCS) described in the Ethernet standard IEEE 802.3-2018 and compliant with Clause 82 of IEEE 802.3ba and Clause 91 of IEEE 802.3bj specification.
The Ethernet PCS IP supports 100G line rates, however other Ethernet PCS speeds are available, such as 1G/2.5G and 10G/25G. The IP provides an interface between the Media Access Control (MAC) and Physical Medium Attachment (PMA) through a 4 lane parallel interface and offers a CGMII interface on the other side.
The PCS IP core is verified using advanced methodologies for RTL design, verification, HW verification and interoperability testing. It has been optimized for size and is a highly tested solution that will fast track any project.
The Ethernet PCS IP supports 100G line rates, however other Ethernet PCS speeds are available, such as 1G/2.5G and 10G/25G. The IP provides an interface between the Media Access Control (MAC) and Physical Medium Attachment (PMA) through a 4 lane parallel interface and offers a CGMII interface on the other side.
The PCS IP core is verified using advanced methodologies for RTL design, verification, HW verification and interoperability testing. It has been optimized for size and is a highly tested solution that will fast track any project.
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Block Diagram of the Ethernet PCS 100G IP Core
Ethernet IP
- 10G-100G MACsec Security Module for Ethernet
- 224G Ethernet PHY in TSMC (N3E)
- 112G Ethernet PHY in TSMC (N7, N5, N3P)
- Multi-protocol SerDes PMA
- 1-56/112G Multi-protocol Serdes (Interlaken, JESD204, CPRI, Ethernet, OIF/CEI)
- PCIe Gen 6 SERDES IP - supports up to 112G LR ethernet with low power and latency