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All Digital Fractional-N PLL for Low-Jitter Clocking - TSMC N6/N7
Perceptia’s DeepSub™ pPLL03F is a PLL featuring low-jitter and compact area suitable for clocking applications with critical timing requirements at frequencies up to 4GHz. It is suitable as a clock source for high performance computing blocks and ADCs/DACs with moderate SNR requirements.
To give SoC designers the maximum flexibility in building complex multi-domain clock systems, pPLL03F is very small (< 0.003 sq mm) and low power (< 5mW). It is well suited to applications with many clock domains where each is driven by their own PLL. To simplify system design, PLL03 has an integrated power supply regulator which allows multiple instances of PLL03 to share common power supplies. Alternatively instances of pPLL03 can share supplies with the blocks that use its output clock.
pPLL03 integrates easily into any SoC design and includes all the views and models required by modern back end flows.
The pPLL03F is built using Perceptia’s second generation all digital PLL technology. This robust technology delivers identical performance regardless of PVT conditions. It consumes a small fraction of the area of an analog PLL whilst maintaining comparable performance.
pPLL03F can be used as an integer-N PLL or as a fractional-N PLL. The fractional-N mode provides a high flexibility to choose the best combination of input and output clock frequencies at the system level.
Perceptia further provides integration support and offers customization and migration services.
To give SoC designers the maximum flexibility in building complex multi-domain clock systems, pPLL03F is very small (< 0.003 sq mm) and low power (< 5mW). It is well suited to applications with many clock domains where each is driven by their own PLL. To simplify system design, PLL03 has an integrated power supply regulator which allows multiple instances of PLL03 to share common power supplies. Alternatively instances of pPLL03 can share supplies with the blocks that use its output clock.
pPLL03 integrates easily into any SoC design and includes all the views and models required by modern back end flows.
The pPLL03F is built using Perceptia’s second generation all digital PLL technology. This robust technology delivers identical performance regardless of PVT conditions. It consumes a small fraction of the area of an analog PLL whilst maintaining comparable performance.
pPLL03F can be used as an integer-N PLL or as a fractional-N PLL. The fractional-N mode provides a high flexibility to choose the best combination of input and output clock frequencies at the system level.
Perceptia further provides integration support and offers customization and migration services.
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Block Diagram of the All Digital Fractional-N PLL for Low-Jitter Clocking - TSMC N6/N7
