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Fractional-N PLLs for Performance Computing
Perceptia’s DeepSub™ pPLL03F is a family of all digital PLLs featuring low-jitter and compact area suitable for clocking applications with critical timing requirements at frequencies up to 4GHz. It is suitable as a clock source for performance computing blocks and ADCs/DACs with moderate SNR requirements.
Perceptia’s second generation pPLL03F family is available on technologies from 5nm to 40nm and across multiple foundry partners. We are continually expanding the range of technologies where it is silicon proven and can quickly port it to other technologies or foundries upon request.
To give SoC designers the maximum flexibility in building complex multi-domain clock systems, pPLL03F is very small (< 0.005 sq mm) and low power (< 2.1mW in GF 22FDX). It is well suited to applications with many clock domains where each is driven by their own PLL. To simplify system design, PLL03 has an integrated power supply regulator which allows multiple instances of PLL03 to share common power supplies. Alternatively instances of pPLL03 can share supplies with the blocks that use its output clock.
pPLL03 integrates easily into any SoC design and includes all the views and models required by modern back end flows.
The pPLL03F is built using Perceptia’s second generation all digital PLL technology. This robust technology delivers identical performance across many processes, regardless of PVT conditions. It consumes a small fraction of the area of an analog PLL whilst maintaining comparable performance.
pPLL03F can be used as an integer-N PLL or as a fractional-N PLL. The fractional-N mode provides a high flexibility to choose the best combination of input and output clock frequencies at the system level.
Perceptia further provides integration support and offers customization and migration services.
Perceptia’s second generation pPLL03F family is available on technologies from 5nm to 40nm and across multiple foundry partners. We are continually expanding the range of technologies where it is silicon proven and can quickly port it to other technologies or foundries upon request.
To give SoC designers the maximum flexibility in building complex multi-domain clock systems, pPLL03F is very small (< 0.005 sq mm) and low power (< 2.1mW in GF 22FDX). It is well suited to applications with many clock domains where each is driven by their own PLL. To simplify system design, PLL03 has an integrated power supply regulator which allows multiple instances of PLL03 to share common power supplies. Alternatively instances of pPLL03 can share supplies with the blocks that use its output clock.
pPLL03 integrates easily into any SoC design and includes all the views and models required by modern back end flows.
The pPLL03F is built using Perceptia’s second generation all digital PLL technology. This robust technology delivers identical performance across many processes, regardless of PVT conditions. It consumes a small fraction of the area of an analog PLL whilst maintaining comparable performance.
pPLL03F can be used as an integer-N PLL or as a fractional-N PLL. The fractional-N mode provides a high flexibility to choose the best combination of input and output clock frequencies at the system level.
Perceptia further provides integration support and offers customization and migration services.
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Block Diagram of the Fractional-N PLLs for Performance Computing IP Core
