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MIPI D-PHY Rx-Only 4 Lanes in TSMC (40nm, 28nm, 22nm, 16nm, 12nm, N7, N6)
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GLink Multi-Slice PCS
GLink Multi-Slice PCS (IGDD2D004A) is a digital IP used to provide data bus alignment between different GLink Slices to ensure consistent data arriving at the RX side in spite of different delays of TX and RX PCS FIFOs of different slices.
GLink Multi-Slice PCS is a configurable design for a specific multi-slice configuration. By specifying number of user interface and the corresponding data bus width, and whether different user interface would be merged into one GLink Slice, a specific GLink Multi-Slice PCS design could be provided, including RTL code with timing constraints and a testbench.
The Multi-Slice PCS is compatible with any revision of GLink IP, and it provides the error indication in case of alignment fail.
GLink Multi-Slice PCS is a configurable design for a specific multi-slice configuration. By specifying number of user interface and the corresponding data bus width, and whether different user interface would be merged into one GLink Slice, a specific GLink Multi-Slice PCS design could be provided, including RTL code with timing constraints and a testbench.
The Multi-Slice PCS is compatible with any revision of GLink IP, and it provides the error indication in case of alignment fail.
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