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H.264 / AVC Baseline Main and High profile decoder
FV264 is a customizable ASIC IP for decoding H.264 compliant streams. H.264 decoder ASIC IP overcomes the limitations of DSPs and other processors based solutions that support limited resolutions and consume lot of power.
FV264 is easy to incorporate in any existing or new SOC or media processors. The core is customizable and is completely compliant to Baseline or main profile. The core has been prototyped on Xilinx Virtex4 based FPGA board for complete functionality.
FV264 is easy to incorporate in any existing or new SOC or media processors. The core is customizable and is completely compliant to Baseline or main profile. The core has been prototyped on Xilinx Virtex4 based FPGA board for complete functionality.
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