NoC Silicon IP for RISC-V based chips supporting the TileLink protocol
H.264 Video Over IP – HD Decoder Subsystem
The subsystem uses the Low-Latency AVC/H.264 Baseline Profile Decoder Core and the RTP and UDPIP, hardware stacks available from CAST. Flexible interfaces allow easy integration of video, memory, and network controllers, and AXI4-Lite slave interfaces allow a host processor to access all control and status registers. An optional custom logic module allows standalone, processor-free operation and provides access to control and status registers via UDP packets. Video and stream data are transferred among the subsystem’s modules using AXI-Stream, making removing or adding modules straightforward.
The subsystem can decode constraint baseline streams, encapsulated in RTP or plain UDP and features, sub-frame latency (no frame buffers are implemented).
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