Hardware IP Protocol Stack

The MW_HPS (Hardware IP Protocol Stack) is the perfect solution for conversion of high speed local interfaces (e.g. USB2, IEEE 1394, PCIExpress, ASI-DVB) to Fast/Giga-Ethernet IP for high speed, persistent throughput and low latency applications. Due to the fact that Software implementation of the IP stack for all these applications is bottlenecked by the processor, MindWay solution is fully hardware-based, overcoming these limits and allowing customers to match whatever throughput requirement. MW_HPS offers both the Receiver and Transmitter side built around the MAC block. To be compliant with the newest MAC blocks, an AXI Stream Interface is provided to interface with the Rx and Tx Buffer, so it is simpler to embed such a type of core in the design. Each port shall be provided with a specific HW protocol handler (e.g. IP2TS, TS2IP, IPTV, FTP handlers). Each handler shall be configured in order to manage the desired channel. At the transmitting side data flows are packetized according to the kind of protocol handler, multiplexed with other outcoming packets and then delivered to the network. Packet Multiplexing is prioritized to minimize loss. At the receiving side, network packets are filtered and delivered to the proper handler that depacketizes them. Some ports are used internally for protocols requiring automatic answer. To have a real plug-and-play solution that performs the main functions helping in network troubleshooting, the following IPv4/IPv6 protocols are supported: ARP, ICMP, ICMPv6 NDP and ICMv6 ECHO. With these protocols the consistency of the link can be immediately asserted. There are also dedicated ports that can bridge standard processor architecture, e.g. based on inexpensive Microblaze™, where a standard software IP stack is implemented. External Ethernet PHY devices can be configured (via MDIO interface) by means of dedicated EMAC_MII Hardware configurator. FPGA netlist only or complete design environment package are deliverable.

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