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NoC Silicon IP for RISC-V based chips supporting the TileLink protocol
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HBM3 Controller
The Rambus HBM3E/3 Controller Cores are designed for use in applications requiring high memory throughput, low latency and full programmability.
The cores accept commands using a simple local interface and translate them to the command sequences required by HBM3E/3 devices. The cores also perform all initialization, refresh and power-down functions. The cores queue up multiple commands in the command queue. This enables optimal bandwidth utilization for both short transfers to highly random address locations as well as longer transfers to contiguous address space.
The command queue is also used to opportunistically perform look-ahead activates, precharges and auto-precharges, further improving overall throughput. The Reorder functionality is fully integrated into the controller command queue increasing throughput and minimizing gate count.
The cores support all HBM3E/3 features, including: data bus inversion (DBI), DQ parity, command / address parity modes, and single-bank refresh and reorder functionality. Add-On Cores such as a Multi-Port Front-End, ECC and AXI can be optionally delivered with the
cores.
The cores are delivered fully integrated and verified with the target HBM3E/3 PHY.
The cores accept commands using a simple local interface and translate them to the command sequences required by HBM3E/3 devices. The cores also perform all initialization, refresh and power-down functions. The cores queue up multiple commands in the command queue. This enables optimal bandwidth utilization for both short transfers to highly random address locations as well as longer transfers to contiguous address space.
The command queue is also used to opportunistically perform look-ahead activates, precharges and auto-precharges, further improving overall throughput. The Reorder functionality is fully integrated into the controller command queue increasing throughput and minimizing gate count.
The cores support all HBM3E/3 features, including: data bus inversion (DBI), DQ parity, command / address parity modes, and single-bank refresh and reorder functionality. Add-On Cores such as a Multi-Port Front-End, ECC and AXI can be optionally delivered with the
cores.
The cores are delivered fully integrated and verified with the target HBM3E/3 PHY.
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