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High performance and low latency hardware accelerated zram/zswap at unmatched power efficiency
The SuperRAM implements a hardware accelerator for zram compression and decompression. SuperRAM implements a ZeroPoint proprietary compression algorithm and is optimized for power efficiency, high throughput and high compression efficiency.
SuperRAM is integrated on the SoC as other hardware accelerators, as a master node on the SoC interconnect. Part of the integration includes a software driver so that the zram crypto-compress API sends a command to the SuperRAM accelerator when there is a software-triggered compression and decompression.
SuperRAM is integrated on the SoC as other hardware accelerators, as a master node on the SoC interconnect. Part of the integration includes a software driver so that the zram crypto-compress API sends a command to the SuperRAM accelerator when there is a software-triggered compression and decompression.
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DRAM IP
- USB 2.0 PHY TSMC 40LPeDRAM
- SMIC 55nm LL SSTL_18/ SSTL_2/ LPDDR/ LVTTL COMBO interface for DRAM application
- SMIC 65nm LL SSTL_18/SSTL_2/LPDDR/LVTTL COMBO interface for DRAM application
- SMIC 65nm LL SSTL_18/ SSTL_2/ LPDDR/ LVTTL COMBO interface for DRAM application
- SMIC 55nm LL LPDDR interface for DRAM application
- SMIC 65nm LL DDR3/DDR2/LPDDR2 COMBO interface for DRAM application