High Performance Media Processor

PACT offers XPP-III cores as synthesizable Verilog RTL Code. XPP-III is built from only a few different components which are linked with pipelined point-to point connections. This allows to arrange and link all IP components (Such as the Array, the FNC-PAEs, Arbiter and DMA Controller) to the required top-level design. Similarily, the size of the array can be scaled easily. The components can be synthesized and routed separately wich may simplify the floorplanning and backend process.

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