Aeonic Generate Digital PLL for multi-instance, core logic clocking
High Speed Access & Test IP PCIE Version
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High Speed Access & Test IP
- High Speed Access & Test IP USB Version
- Silicon-proven, High Density and Low Power Static Random Access Memories
- Single Port SRAM compiler - Memory optimized for high density and speed - Dual Voltage - Compiler range up to 640 kbits
- High Performance 8051 Compatible CPU Core
- Interlaken, 40G, 8 Lanes
- Clock Delay Monitor IP