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I2C I/O Pad Set
The I2C library provides open-drain bi-directional I/O cells designed for the I2C two-line interface. It is compliant with the I2C-bus specification – UMC10204 I2C-bus specification and user manual, Rev.4 – 13 February 2012, NXP.
The design supports the Sm, Fm and Fm+ modes of operation at the I2C bus operating voltage (VDDP) of either extended range 3.3V or standard 1.8V logic.
These libraries are offered at both 16nm and a 12nm shrink. They
are available in a staggered CUP wire bond implementation with a flip chip option.
To utilize these cells in the pad ring, an additional library is required – 1.8V Support: Power. That library contains the power cells, the POC cell, and a rail splitter to isolate the I2C cells in their own power domain as recommended. It also contains an input-only buffer, isolated analog I/O, and a full complement of power cells along with corner and spacer cells to assemble a complete pad ring by abutment. The rail splitter allows multiple power domains to be isolated in the same pad ring while maintaining continuous VDD/VSS for robust ESD protection.
The design supports the Sm, Fm and Fm+ modes of operation at the I2C bus operating voltage (VDDP) of either extended range 3.3V or standard 1.8V logic.
These libraries are offered at both 16nm and a 12nm shrink. They
are available in a staggered CUP wire bond implementation with a flip chip option.
To utilize these cells in the pad ring, an additional library is required – 1.8V Support: Power. That library contains the power cells, the POC cell, and a rail splitter to isolate the I2C cells in their own power domain as recommended. It also contains an input-only buffer, isolated analog I/O, and a full complement of power cells along with corner and spacer cells to assemble a complete pad ring by abutment. The rail splitter allows multiple power domains to be isolated in the same pad ring while maintaining continuous VDD/VSS for robust ESD protection.
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