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180nm MTP Non Volatile Memory for Standard CMOS Logic Process
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I2C Slave Controller w/FIFO (AXI Bus)
The Digital Blocks DB-I2C-S-AXI Controller IP Core interfaces an ARM, MIPS, PowerPC, ARC or other high performance microprocessor via the AMBA 4/3 AXI System Interconnect Fabric to an I2C Bus. The I2C is a two-wire bidirectional interface standard (SCL is Clock, SDA is Data) for transfer of bytes of information between two or more compliant I2C devices.
The DB-I2C-S-AXI is a Slave I2C Controller that controls the Transmit or Receive of data to or from external Master I2C devices.
The DB-I2C-S-AXI supports AXI4-Lite, AXI4, AXI3 AMBA specifications.
The DB-I2C-S-AXI is a Slave I2C Controller that controls the Transmit or Receive of data to or from external Master I2C devices.
The DB-I2C-S-AXI supports AXI4-Lite, AXI4, AXI3 AMBA specifications.
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Block Diagram of the I2C Slave Controller w/FIFO (AXI Bus)
I2C Slave Controller IP
- I2C and SPI Master/Slave Controller
- I2C Master/Slave Controller Core IP
- I2C Master / Slave Controller w/FIFO (AHB & AHB-Lite Bus)
- I2C Master / Slave Controller w/FIFO (APB Bus)
- Hs-Mode I2C Controller - 3.4 Mbps, Master / Slave w/FIFO
- I2C Slave Controller - Low Power, Low Noise Config of User Registers