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I3C Master / Slave Controller w/FIFO (APB Bus)
The Digital Blocks DB-I3C-MS-APB Controller IP Core interfaces a microprocessor via the AMBA APB Bus to an I3C Bus, compliant to the MIPI I3C – Improved Inter Integrated Circuit specification.
The I3C is a two-wire bidirectional interface standard (SCL is Clock, SDA is Data) for transfer of bytes of information between two or more compliant I3C devices as well as legacy I2C Slave devices, typically with a microprocessor behind the Master/Slave controller and one or more Master or slave devices on the I3C bus.
Digital Blocks offers I3C Controller Master/Slave, Master only, and Slave only IP with AXI / AHB / APB Interfaces. In addition, besides interfacing to a CPU, the I3C Controllers can transfer blocks of data directly between System Memory or Registers and the I3C Bus.
The I3C is a two-wire bidirectional interface standard (SCL is Clock, SDA is Data) for transfer of bytes of information between two or more compliant I3C devices as well as legacy I2C Slave devices, typically with a microprocessor behind the Master/Slave controller and one or more Master or slave devices on the I3C bus.
Digital Blocks offers I3C Controller Master/Slave, Master only, and Slave only IP with AXI / AHB / APB Interfaces. In addition, besides interfacing to a CPU, the I3C Controllers can transfer blocks of data directly between System Memory or Registers and the I3C Bus.
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Block Diagram of the I3C Master / Slave Controller w/FIFO (APB Bus)
