Implementation of the RISC-V RV64GC ISA

Cortus have applied their many years of processor design expertise to the RISC-V ISA. Concentrating on the needs of the embedded designer and leveraging the success of their APS family of processors.

The FPS69V processor is an implementation of the RISC-V ISA RV64GC, with the full integer instruction set, compressed instructions and multiply and divide. It also has single and double precision floating point. In addition it implements the privilege features with Machine and User modes.

The Cortus FPS69V processor features a Harvard architecture with AXI4 bus interfaces. This ensures wide compatibility with other peripheral IP, allowing the standard peripherals from Cortus to be complemented by other IP.

Full debug support is implemented through Cortus’ standard debug interface and tools (GDB and OpenOCD).

• see the entire Implementation of the RISC-V RV64GC ISA datasheet
• get in contact with Implementation of the RISC-V RV64GC ISA Supplier