English
You are here:
Input 2MHz~16MHz, output 16~72MHz and 72MHz~200MHz, 1.08~1.32V PLL; UMC 55nm Low Power Process.
Input 2MHz~16MHz, output 16~72MHz and 72MHz~200MHz, 1.08~1.32V PLL; UMC 55nm Low Power Process.
View Input 2MHz~16MHz, output 16~72MHz and 72MHz~200MHz, 1.08~1.32V PLL; UMC 55nm Low Power Process. full description to...
- see the entire Input 2MHz~16MHz, output 16~72MHz and 72MHz~200MHz, 1.08~1.32V PLL; UMC 55nm Low Power Process. datasheet
- get in contact with Input 2MHz~16MHz, output 16~72MHz and 72MHz~200MHz, 1.08~1.32V PLL; UMC 55nm Low Power Process. Supplier
Analog IP
- UCIe/BoW BlueLynx™ Dual Mode PHY and subsystem IP for chiplet interconnect
- Analog Front End: 16x 12-bit 200 MSPS ADCs, 14x Voltage DACs, 4x 250 MSPS DACs, 4x TVM, LDO
- Analog Front End: 2x 12-bit 4 GSPS IQ ADCs, 2x 12-bit 8GSPS IQ DACs, bandgap, temp sensor, PLL, 4 x LDO
- Analog I/O - low capacitance, low leakage
- Bluetooth Low Energy (BLE) analog PHY
- Analog Front End: 8x 12-bit 2 GSPSADCs, 4x 12-bit 200 MSPS ADCs, TVM, PLL, LDO