English
Adaptive Clock Generation Module for DVFS and Droop Response
You are here:
LDPC Error Correction Core IP (for SSD, silicon proven, UBER<1E-17)
YEESTOR’s LDPC IP Core (Alcyone) delivers industry-leading error correction performance to support 2S/3D SLC/MLC/TLC/QLC NAND for each application from mobile, client, and enterprise NAND flash controller markets. Alcyone provides a highly efficient pure hardware engine with standard AXI interface for easily integration. Based on several patented technology of YEESTOR, the Alcyone LDPC IP provides very high throughput and error correction capability with low area and power consumption. YEESTOR’s LDPC IP was silicon-proven in industrial/enterprise PCIe SSD, USB, and EMMC application.
View LDPC Error Correction Core IP (for SSD, silicon proven, UBER<1E-17) full description to...
- see the entire LDPC Error Correction Core IP (for SSD, silicon proven, UBER<1E-17) datasheet
- get in contact with LDPC Error Correction Core IP (for SSD, silicon proven, UBER<1E-17) Supplier
Block Diagram of the LDPC Error Correction Core IP (for SSD, silicon proven, UBER<1E-17)
