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Linear Regulator, Low Noise optimized for sensitive application such as RF or PLL blocks
nLR-Charny-ref-[1.62-3.63]-[0.8-2.5]-Ixx.02, as any Power Management Virtual Component designed by Dolphin Design, is readily retargetable toward any submicron CMOS process.
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Block Diagram of the Linear Regulator, Low Noise optimized for sensitive application such as RF or PLL blocks
LDO IP
- LDO Voltage Regulator, 30 mA, Adjustable 0.45 V to 0.9 V Output
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- Analog Front End: 16x 12-bit 200 MSPS ADCs, 14x Voltage DACs, 4x 250 MSPS DACs, 4x TVM, LDO
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- LDO Linear Voltage Regulator
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