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Aeonic Generate Digital PLL for multi-instance, core logic clocking
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Linear Regulator, Low Noise optimized for sensitive application such as RF or PLL blocks
nLR-Charny-ref-[1.62-3.63]-[0.8-2.5]-Ixx.02, as any Power Management Virtual Component designed by Dolphin Design, is readily retargetable toward any submicron CMOS process.
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Block Diagram of the Linear Regulator, Low Noise optimized for sensitive application such as RF or PLL blocks
LDO IP
- LDO Voltage Regulator, 30 mA, Adjustable 0.45 V to 0.9 V Output
- LDO Voltage Regulator, 250 mA, Adjustable 0.45 V to 0.9 V Output
- Analog Front End: 16x 12-bit 200 MSPS ADCs, 14x Voltage DACs, 4x 250 MSPS DACs, 4x TVM, LDO
- Analog Front End: 2x 12-bit 4 GSPS IQ ADCs, 2x 12-bit 8GSPS IQ DACs, bandgap, temp sensor, PLL, 4 x LDO
- LDO Linear Voltage Regulator
- Ultra-low quiescent LDO voltage regulator in TSMC 22ULL