Link Layer Controller

Features

• Fully compliant with IEEE 1394-1995 Standards. .
• Half Duplex Independent; Transmit and Receive Data Path controlled by Rx Tx Controller.
• 32-bit Generic Host Bus Interface.
• Has a hand-shaking signal for Host.
• Full Implementation of Link Core.
• Supports Asynchronous, Isochronous and Cycle start packet Transmit and Receive.
• Automatic 32-bit CRC generation and error detection. CRC
• Cycle Master cable.
• Supports all required 11 Packet Formats; 9 Asynchronous and 2 Isochronous as per standard.
• 2 Kbytes Transmit and Receive FIFO or Buffer.
• PHY Link Interface conforms to the specifications described in the Annex J of the IEEE 1394-1995 standard.
• Supports 100/200 and 400 Mbps bus rates.
• Single clock domain throughout the system.