Lossless MJPEG Decoder
At the center of the logiJPGD-LS IP core is a decoder block, based on the Huffman coding algorithm. It works with the color component precision up to 12 bits and supports standard JPEG headers. The logiJPGD-LS IP Core supports decompression of JPEG LS frames with one color component, the so-called color plane. A full multi-color video decompression requies division of JPEG encoded multi-color videos (i.e. Bayer, YUV, RGB) in separated JPEG LS frames per color component – color planes. One logiJPGD-LS IP core can sequentially decompress all color planes to generate multi-color video output. Alternatively, multiple logiJPGD-LS IP cores instantiated in a parallel can decompress all input color planes at once.
In typical IP applications, a previously encoded (compressed) MJPEG video is decoded (de-compressed) and transferred to the IP core’s output. The de-compressed video can be further processed by the next block in the video pipeline, or with an additional Xilinx IP such as AXI Video DMA, directly stored to off-chip memory. The logiJPGD-LS IP Core works smoothly with Xylon's logjJPGE-LS Lossless MJPEG Encoder IP Core, as well as other lossless MPJEG encoders compatible with the Annex H of the ISO/IEC 10918-1 JPEG Standard. Xylon also offers a pair of lossy MJPEG compression (logiJPGE) and decompression (logiJPGD) IP cores which give the user the ability to tune the level of compression used.
View Lossless MJPEG Decoder full description to...
- see the entire Lossless MJPEG Decoder datasheet
- get in contact with Lossless MJPEG Decoder Supplier