English
You are here:
LVDS TX Combo TTL PHY
Innosilicon LVDS implements LVDS TIA/EIA protocol. Normally, Innosilicon LVDS contains four 7-bit parallel-load serial-out shift registers, a 7X clock PLL, and five Low-Voltage Differential Signaling (LVDS) line drivers in a single integrated circuit.
When transmitting, parallel data and pin_pdata_* are each loaded into registers upon the edge of the input clock signal (pin_pixel_clk). The frequency of pin_pixel_clk is multiplied seven times, and then used to unload the data registers in 7-bit slices and serially. The four serial streams and a phase-locked clock (CLKP/CLKN) are then output to LVDS output drivers. The frequency of CLKP/CLKN is the same as the input clock, pin_pixel_clk.
In addition, Innosilicon LVDS could extend from 5 lanes to N lanes (N is required by the customer). Therefore, the TTL lines extend respectively.
When transmitting, parallel data and pin_pdata_* are each loaded into registers upon the edge of the input clock signal (pin_pixel_clk). The frequency of pin_pixel_clk is multiplied seven times, and then used to unload the data registers in 7-bit slices and serially. The four serial streams and a phase-locked clock (CLKP/CLKN) are then output to LVDS output drivers. The frequency of CLKP/CLKN is the same as the input clock, pin_pixel_clk.
In addition, Innosilicon LVDS could extend from 5 lanes to N lanes (N is required by the customer). Therefore, the TTL lines extend respectively.
View LVDS TX Combo TTL PHY full description to...
- see the entire LVDS TX Combo TTL PHY datasheet
- get in contact with LVDS TX Combo TTL PHY Supplier