English
Scalable UHD H.264 Encoder - Ultra-High Throughput, Full Motion Estimation engine
You are here:
MIPI D-PHY DSI RX (Receiver) in TSMC 110G
The MXL-DPHY-DSI-RX-T-110G is a high-frequency, low-power, low-cost, source-synchronous, Physical Layer compliant with the MIPI Alliance Standard for D-PHY. The IP is configured as a MIPI slave with maximum of 5 lanes: 1 Clock lane and 4 data lanes, which make it suitable for display serial interface applications (DSI). The High-Speed signals have a low voltage swing, while Low-Power signals have large swing. High-Speed functions are used for
High-Speed Data traffic while low power functions are mostly used for control.
High-Speed Data traffic while low power functions are mostly used for control.
View MIPI D-PHY DSI RX (Receiver) in TSMC 110G full description to...
- see the entire MIPI D-PHY DSI RX (Receiver) in TSMC 110G datasheet
- get in contact with MIPI D-PHY DSI RX (Receiver) in TSMC 110G Supplier
MIPI D-PHY Receiver IP
- MIPI DSI Receiver Controller v1.3
- MIPI CSI-2 controller Receiver v 2.1, Compatible with MIPI C-PHY v1.2 & DPHY v2.1.
- MIPI D-PHY Tx IP, Silicon Proven in TSMC 22ULP
- MIPI DSI-2 Receiver Controller v1.0
- MIPI D-PHY CSI-2 RX (Receiver) in Samsung 28FDSOI
- MIPI C-PHY/D-PHY Combo DSI RX (Receiver) IP in TSMC 28HPC+