MIPI D-PHY for TSMC

D-PHY physical layer

Developed by experienced teams with industry-leading domain expertise and extensively validated by multiple hardware platforms, the PHY IP is silicon-proven and shipping in high volume in multiple mobile devices. The PHY IP is engineered to quickly and easily integrate into any design, and to connect seamlessly to a Cadence or third-party PPI compliant controller. Implemented on several popular semiconductor processes, the PHY IP provides a cost-effective, low-power solution for demanding mobile applications. The IP is a mixed-signal PHY consisting of a D-PHY transmitter and a D-PHY receiver. The PHY IP is developed and validated to reduce risk for designers so that their system on chip (SoC) can be first-time right. Developed and available early in the life-cycle of the most advanced semiconductor process nodes, the PHY IP is designed to be robust under varying signal strength and noise conditions. The PHY IP is part of the comprehensive Cadence Design IP portfolio comprised of interface, memory, analog, and systems and peripherals IP

• see the entire MIPI D-PHY for TSMC datasheet
• get in contact with MIPI D-PHY for TSMC Supplier