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MIPI D-PHY Tx IP, Silicon Proven in TSMC 28HPC+
The MIPI D-PHY Tx IP Core fully complies with version 1.2 of the D-PHY specification. It supports the Display Serial Interface and the MIPI Camera Serial Interface (CSI-2) protocols. Operating as a Tx PHY, it consists of one clock lane and four data lanes. The digital backend manages I/O operations, while the analog frontend generates and receives electrical signals. Additionally, it features an auto-calibrating internal termination resistor. This MIPI DSI PHY encompasses a MIPI D-PHY Tx IP Core incorporating a PLL, a Clock Lane, four Data Lanes, and the option to utilize the D-PHY as a GPIO bank with a 5V tolerance.
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Block Diagram of the MIPI D-PHY Tx IP, Silicon Proven in TSMC 28HPC+
MIPI D-PHY Tx IP Core IP
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