MIPI DSI TX Controller

The MIPI DSI Transmitter IP is an all-digital design consisting of a Redistribution Layer to interface to one or more Display Modules, external register interface for configuration of the Transmitter IP and connected D-PHY Lane Modules, and error reporting, Lane Management Layer for distributing the DSI stream among the connected D-PHY Lane Modules, DSI Protocol Layer for protocol functions, and Arbitration Layer for arbitrating among the various data and command streams.

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