Modern, high performance Audio DSP, optimized for far-field noise reduction and Artificial Intelligence speech recognition
Ceva-BX2 uses quad 32X32-bit MACs and octal 16X16-bit MACs, with enhanced capability for supporting 16×8-bit and 8×8-bit MAC operations.
The Ceva-BX2 is using an 11-stage pipeline and 5-way VLIW micro-architecture, it offers parallel processing with dual scalar compute engines, load/store and program control that reaches a speed of 2 GHz at a TSMC 7nm process node.
The Ceva-BX2 Instruction Set Architecture (ISA) incorporates support for Single Instruction Multiple Data (SIMD) as well as optional floating point units for high accuracy algorithms.
The Ceva-BX2 is accompanied by a comprehensive software development tool chain, including:
* Advanced LLVM compiler
* Eclipse based debugger
* DSP and neural network compute libraries
* Neural network frameworks support
* Real Time Operating Systems (RTOS)
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Block Diagram of the Modern, high performance Audio DSP, optimized for far-field noise reduction and Artificial Intelligence speech recognition
Audio DSP IP
- Modern Audio DSP, designed for battery operated, high-performance, audio and voice applications
- Multifunctional DSP Architecture for High-Performance, Low-Power Audio/Voice/Sensing and Wireless Communication Applications
- Low-power, low-gate-count, highly-configurable DSP core for audio and control processing
- I2S/Left-Justified/TDM Digital Audio Interface
- High Performance Scalable Sensor Hub DSP Architecture
- Video DMA Core