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Multilayer Configurable Display Controller
The IQ-DispML is a multi-layer, fully software configurable display controller IP core. It performs continuous refresh of graphical flat panel displays (TFT LCD, AMOLED) from the designated frame buffers located in a memory device mapped to the system bus.
Multiple layers are blended into a single image, which is outputted to the display. SDRAM and SRAM devices are supported as frame buffers, depending on the bandwidth requirements.
IQ-DispML is designed to provide an optimum tradeoff of performance and resource utilization in FPGA devices while retaining a high degree of configurability. The IP core can be additionally scaled down at compile time by reducing the number of layers, bus widths and fixing timing parameters, allowing the user to fully optimize the IQ-DispML for a specific configuration.
Multiple layers are blended into a single image, which is outputted to the display. SDRAM and SRAM devices are supported as frame buffers, depending on the bandwidth requirements.
IQ-DispML is designed to provide an optimum tradeoff of performance and resource utilization in FPGA devices while retaining a high degree of configurability. The IP core can be additionally scaled down at compile time by reducing the number of layers, bus widths and fixing timing parameters, allowing the user to fully optimize the IQ-DispML for a specific configuration.
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Block Diagram of the Multilayer Configurable Display Controller IP Core
